The present invention relates to a semiconductor memory constituted by, for example, insulated gate type field effect transistors, such as MOS transistors, and, in particular, to a static semiconductor memory using static type cells as its memory cells.
With regard to semiconductor memories, as the memory capacity increases due to recent improvement in process technology, a data line pair becomes longer, thus increasing the load capacity of the data line that should be driven by a memory cell. The increase in loading capacity reduces data readout speed. According to prior art memories, to reduce the load capacity to be driven by a memory cell a memory cell array is divided into a plurality of sections. This type of memory, available today, has a plurality of section data line pairs for each section. Each of the section data line pairs in each section is connected to a plurality of memory cells to be accessed.
FIG. 1 is a block diagram illustrating the structure of a semiconductor memory having its memory array divided into a plurality of sections. In FIG. 1, the memory is assumed to be of a one-bit readout type for explanatory simplicity. A memory cell array 80 is divided into a plurality of sections 81-1 to 81-n. Within each section 81-i (i=1 to n), static memory cells 82-11 to 82-1n are arranged in a two-dimensional array for each section word line WLi (i=1 to n). Referring now to section 81-1 as an example, the semiconductor memory will be explained.
Each memory cell 82-1i (i=1 to n) is coupled to word line WL1 and bit line pair BL-1i, BL-1i (i=1 to n), each bit line pair being coupled to load circuit 83-1.
Word line WL is activated by a row decoder (not shown), and is arranged over the entire section. A signal on word line WL and section designation signal SDi (i=1 to n) are supplied to a section gate 85-i (i=1 to n). Section designation signal SD1 output from section selector 84-1 is activated only when section 81-1 is designated. Based on the output of gate 85-1, only the word line WL1 in the selected section 81-1 is activated. Data are read out from all of memory cells 82-1i (i=1 to n) coupled to this activated section word line WL1 in the selected section, and each signal pair associated with the read out data is transferred to its associated bit line pair BL-1i, BL-1i (i=1 to n).
Column select gate 86-1i (i=1 to n) is controlled on the basis of column designation signal CD, and one signal pair is selected from the signal pairs on bit line pair BL-1i, BL-1i (i=1 to n) in accordance with signal CD and is sent to section data line pair SDL-1, SDL-1. The signal pair transferred to section data line pair SDL-1, SDL-1 is supplied to section sense amplifier 87-1. Amplifier 87-1, provided for each section data line pair SDL-1, SDL-1, is selectively activated by section sense amplifier activation signal SSA1 output from section selector 84-1. The output of inactive amplifier 87-1 is rendered to be a high impedance. The signal pair output from sense amplifier 87-1 is transferred on main data line pair MDL, MDL commonly running over the entire section. The signal pair on line pair MDL, MDL is supplied to main sense amplifier 88 located near an output buffer (not shown) in a chip. A signal pair amplified by sense amplifier 88 is latched by latch circuit 89 and is transferred to the output buffer as readout data D0.
FIG. 2 is a detailed circuit diagram of the structure of each section of the aforementioned conventional memory.
As illustrated, memory cell 82-11 comprises flip-flop 93 and MOS transistors 94 and 95 serving as transfer gates. Flip-flop 93 is constituted by cross-coupling the input and output terminals of two inverters 91 and 92, the input of one inverter being coupled to the output of the other and vice versa. Each inverter comprises a high resistance resistor and a driving MOS transistor. MOS transistor 94 is coupled between one output terminal of flip-flop 93 and bit line BL-11, and MOS transistor 95 coupled between the other output of flip-flop 93 and bit line BL-11. The gates of two MOS transistors 94 and 95 are coupled to section word line WL1 in section 81-1.
Column select gate 86-11 is coupled between bit line pair BL-11, BL-11 and section data line pair SDL-1, SDL-1, and comprises two MOS transistors 96 and 97 whose gates are supplied with column select signal CD.
Section sense amplifier 87-1 is a current mirror parallel type sense amplifier and is separated into driver section 87-1A and load section 87-1B. Driver section 87-1A is further divided into drivers 106A and 106B, each having N-channel driving transistors 101, 102, N-channel switching transistors 103, 104 and an N-channel current control transistor 105. Driving transistors 101 and 102 respectively receive the signals on section data line pair SDL-1 and SDL-1 at their gates. Switching transistors 103 and 104 receive section sense amplifier activation signal SSA1 at their gates. Similarly, load section 87-1B is separated into two current mirror type load circuits 113A and 113B, each comprising two P-channel MOS transistors 111 and 112. In sense amplifier 87-1, only driver section 87-1A is provided separately for each section data line pair. In contrast, only one load section 87-1B is provided commonly for all of the section sense amplifiers.
To use this type of section sense amplifier, reference main data line pair MDLR, MDLR is added to the intrinsic main data line pair MDL, MDL.
In the aforementioned conventional memory, the memory cell array is divided into a plurality of sections and one section is selectively activated for data readout. A signal pair corresponding to the read-out data is amplified by sense amplifier 87-i (i=1 to n) and is output on main data lines MDL, MDL. Then, the amplified signal pair on the line pair MDL, MDL is amplified by main sense amplifier 88 to have a CMOS drive level and then is latched by latch 89.
Since section data line pairs SDL-i, SDL-i (i=1 to n) are separately arranged for each section in above-mentioned memory, the load capacity can be smaller as compared with the case where the signal pair on each bit line pair BL-ii, BL-ii (i=1 to n) is directly transferred to main data line pair MDL, MDL through corresponding column select gate 86-ii (i=1 to n). Therefore, it is possible to directly drive a memory cell that is capable of driving just a small current. In addition, the data readout speed can be increased to some degree.
However, the greater the memory capacity becomes, the greater the number of sections. Therefore, the load capacity or the wiring capacity of main data line pair MDL, MDL is increased. In addition, the sum of the drain junction capacities of switching transistors 103 and 104 coupled to main data line pair MDL, MDL increases with an increase in the quantity of the sections. This naturally increases the load capacity that section sense amplifiers 87-i drive. Consequently, the time-dependent signal variation speed on main data line pair MDL, MDL gets slower, thus reducing the data readout speed.
As a solution to this problem, driving transistors 101, 102 in section sense amplifier 87-1 may be designed to be larger; however, the sizes of switching transistors 103 and 104 need to be increased, in which case the drain junction capacities increase further. If the sizes of the transistors in section sense amplifier 87-i are increased, therefore, the data readout speed cannot be improved. Furthermore, the increase in transistor size increases the power consumption of section sense amplifier 87.
As should be understood from the above, in the conventional static semiconductor memory, an increase in memory capacity reduces the data readout speed.